1. Field of the Invention
The present invention relates to a method and apparatus for controlling transfer of data and, more particularly, to a method and apparatus for controlling transfer of data using a burst transfer method which is generally performed in a data processing system.
2. Description of the Related Art
FIG. 1 is a block diagram of a part of a conventional data processing system in which a burst transfer operation is performed. In FIG. 1, an arithmetic processor 1 processes data. A memory 2 is an external memory comprising a dynamic random access memory (DRAM) having a capacity of 4 giga-bytes and a burst transfer mode. An external address bus 3 has a 32-bit structure. An external address bus 4 has a 64-bit structure.
FIGS. 2A-2E represent is a timing chart of a burst transfer operation performed between the arithmetic processor 1 and the external memory 2. FIG. 2A shows an external clock signal. FIG. 2B shows the state of a bus request signal output from the arithmetic processor 1 for requesting use of a bus. FIG. 2C shows a state of a bus acknowledge signal provided to the arithmetic processor 1 to permit use of a bus. FIG. 2D shows the state of the external address bus 3. FIG. 2E shows the state of the external address bus 4.
In the example shown in FIGS. 2A-2E, an address A1 is output to the external address bus 3 as a start address of the first cycle of burst transfer after a permission of use of the bus is provided upon the request for use of the bus output from the arithmetic processor 1. Then, the sets of data D1-D4 are sequentially output to the external address bus 4 in the order D1.fwdarw.D2.fwdarw.D3.fwdarw.D4. Thus, a burst transfer (a store transfer for the external memory 2 or a load transfer for an internal memory of the arithmetic processor 1) is performed for the sets of data D1-D4.
Thereafter, an address A2 is output to the external address bus 3 as a start address of the second cycle of burst transfer. Then, the sets of data D5-D8 are sequentially output to the external address bus 4 in the order D5.fwdarw.D6.fwdarw.D7.fwdarw.D8. Thus, a burst transfer is performed for the sets of data D5-D8.
Thereafter, an address A3 is output to the external address bus 3 as a start address of the third cycle of burst transfer. Then, the sets of data D9-D12 are sequentially output to the external address bus 4 in the order D9.fwdarw.D10.fwdarw.D11.fwdarw.D12. Thus, a burst transfer operation is performed for the sets of data D9-D12.
In the above-mentioned example, a number of consecutive sets of data transferred by a single burst transfer, which is referred to as a burst length, is 4. In this case, the period for calculating the address is one fourth of that of a case where the address is output for each of the sets of data D1-D12 for each clock pulse. This allows the design of a high-speed data processing system.
In the conventional burst transfer, the word length typically comprises several bytes, for example, 4 bytes or 8 bytes, so as to perform the data transfer on the word basis. Thus, it is no longer standard to perform a data transfer in which the transfer is started from an arbitrary byte, as a start address, in a single word.
When a plurality of burst transfer operations starting from an arbitrary byte as a start address are performed consecutively, it is required to calculate the start address for each clock signal pulse if the start address for the second and later burst transfer operations is determined by counting the number of words which have been transferred. Thus, there is a problem in that a high-speed adder for the address calculation is needed.